AD9361第一个例程

ADI Reference Designs HDL User Guide

AD9361 No-OS Software

AD9361起步例程

平台 zc706

开发套件:AD-FMCOMMS3-EBZ

软件:vivado 13.4

 

HDL Sources

ADI公司提供了硬件驱动库,可在github上获得,连接如下https://github.com/analogdevicesinc/hdl/tree/hdl_2014_r1

(这里有几个不同的版本,dev不建议使用,根据自己用的软件环境选择合适的源码)

Repository Structure

root

The root directory.

root

The library consists of cores specific to a certain device or function. The cores are just a group of HDL files consists of device specific interface, register map, status and monitoring interface. A project may use one or more such cores.

root

The projects consists of embedded systems for a certain platform. As an example AD-FMCOMMS1 is available on ZC706, ZC702 and Zed platforms.

下载方法

可以使用git工具将HDL源码克隆到本地,也可以将整个库文件打包成zip下载

这里采用第二种方法,点击download zip,将下载库。

Building HDL

 

1) 将下载的源码hdl-hdl_2014_r1.zip解压,后改目录名为hdl,拷贝到c:/github/目录下(这里为了个官方一致,方便以后操作)。

2) 打开C:\github\hdl\library\axi_ad9144 你会发现

这些文件,这些库是未编译的,所以要用vivado对用到的lib进行编译,

编译方法:打开vivado软件, 利用TCL控制台

如编译axi_ad9144

cd c:/github/hdl/library/axi_ad9144

回车后 进入该路径,输入下一个命令,运行tcl脚本

source ./axi_ad9144_ip.tcl

你会看到软件进入工程界面,这里对其不做操作,待运行完,对工程进行保存

 

http://wiki.analog.com/_media/resources/fpga/docs/hdl/vivado_library_1.jpg?w=800&tok=7bbf9f

http://wiki.analog.com/_media/resources/fpga/docs/hdl/vivado_library_2.jpg?w=800&tok=a64c61

这里需要编译用到的lib库,我们用到ad9361,为了确保后期编译平台例程时用到的库都被编译,我采用的方法是将除和ad芯片相关的库外,对其它含tcl脚本的分别进行了编译(有的不能编译,除外)。

Projects

当库文件编译好后,接下来我们建立所用的工程。

和编译库的方法相同,打开vivadoTCL控制台输入一下命令

cd c:/github/hdl/projects/fmcomms2/zc706

回车后运行tcl脚本

source ./system_project.tcl

你会看到软件进入工程界面,这里对其不做操作,待运行完,对工程进行保存

The script will create a board design in IPI, generate all the IP targets, synthesize the netlist and implementation. It also exports the hardware to SDK

建立

http://wiki.analog.com/_media/resources/fpga/docs/hdl/vivado_library_1.jpg?w=800&tok=7bbf9f

导出到SDK

运行生成二进制文件流,

选择 file->export->export hardware for SDK

至此,HDL部分建立完成

下载软件库

ADI公司提供了no-os软件库,可在github上获得,连接如下

https://github.com/analogdevicesinc/no-OS/tree/2014_R1

 

下载方法

HDL下载方法

 

建立工程

前面导出的SDK . C:\github\hdl\projects\fmcomms2\zc706\fmcomms2_zc706.sdk\SDK路径下面

·         Go to File→New→Application project

 New Application Project

·         Use a new hardware platform, so choose Create new in Hardware Platform

 New Platform

·         In Target Hardware Specification browse the location of SDK_Export\hw\system.xml and click Finish

 New Hardware Project

·         Then give a name to the project and click Next

 Project Name

·         In the next window choose Empty Application and click Finish

 Available Templates

·         Now the project without source code looks like this

 Empty Project

·         导入源文件将下载的软件库解压,进入no-OS-2014_R1\ad9361\sw文件下,将*.c *.h的文件拷贝到工程目录src下,最简单的拷贝方法就是选中文件Ctrl+c 然后在软件上选择srcCtrl+v

·         同样的方法进入no-OS-2014_R1\ad9361\sw\platform_generic 将里面的文件拷贝到src里面来。

·         no-OS-2014_R1\ad9361\sw\console_commands里面的文件拷贝到src里面来。

 SDK Project

·          Project→Build Automatically 当文件出现错误时,检查头文件引用路径(如command.c #inlcude "../ad9361_api.h" 找不到,修改引用到正确的路径)

 Project Explorer

·         为了能够用xilinx平台,你应该去掉#define XILINX_PLATFORM常量宏的注释。宏在main.c的头部。如果你要用console command #define CONSOLE_COMMANDS也应该去掉注释。

 Project Explorer

 

 

 Program FPGA

·         Then choose this bitstream and press Program

 Program FPGA with bitstream

·         This window will appear next.

 Program FPGA progress

·         Afterwards a Run Configuration must be created and then press Run

 Run Configuration

·         The output of the example program can be viewed in the SDK console by enabling the Connect STDIO Console option and setting the baud rate of the UART port to 115200.

 STDIO configuration

As an alternative an UART terminal can be used to capture the output of the example program. The number of used UART port depends on the computer's configuration. The following settings must be used in the UART terminal:

·         Baud Rate: 115200bps

·         Data: 8 bit

·         Parity: None

·         Stop bits: 1 bit

·         Flow Control: none

这个例程的功能:系统配置成两通道正弦信号发生,通过2.4GHz的载波将信号传输到接收通道。接受通道收到信号变为基带信号, 通过ADC数字化。I Q 通道的取样值可以用  Vivado Hardware Manager.观察,遵循以下步骤查看正弦波

·         第一,确保板子已经下了程序,并且程序正在运行

·         然后打开VivadoFlow→Open Hardware Manager

 Open Hardware Manager

 

·         In the new window select Open a new hardware target

 Open New Hardware Target

·         Then click Next 4 times and then Finish

 Open New Hardware Target Server name Select Target  Set Properties Open New Hardware Target 

·         This is how the Vivado Hardware Manager looks like. Now go to Probes file.

 Device Properties

·         And browse for the folder where the project was complied ../fmcomms2_board.runs/impl_1/debug_nets.ltx

 Specify Probes File

·         Then do a right click on the active target and choose Refresh Device

 Refresh Device

·         Afterwards do another right click on the active target and choose Run Trigger

 Run Trigger

·         This is how the 48 digital signals look like. Now we have to compose the sinewaves.

 ILA Signals

·         First select the first 12 signals, do a right click and choose New Virtual Bus

 New Virtual Bus

·         Then give a name to that virtual bus

 Specify Virtual Bus Name

·         In order to see a sinewave you have to right click on the name of the virtual bus, choose Analog for Waveform Style option.

 Analog Waveform Style

·         Now you can see a sinewave, but the radix is not the good one. In order to have the right radix, you must choose Signed Decimal forRadix.

 Signed Decimal Radix

·         Now the signal looks like a sinewave

 One Virtual Bus Sinewave

·         And after you did the same steps for the other 3×12 remaining signals, you should have 4 sinewaves composed of 48 signals. ON FMCOMMS2 there are 2 channels, each channel with 2 signals (I and Q).

 4 Virtual Buses Sinewaves